🎓 Lesson 10
D5
Diagnosing CAN Bus Timing Violations in VT Networks
CAN bus timing violations in VT networks occur when messages arrive too early or too late on the communication line, causing the Virtual Terminal to misinterpret or reject commands from the machine controller.
🎯 Learning Objectives
- ✓ Calculate nominal bit time and sample point position using oscillator tolerance and network parameters
- ✓ Analyze CAN bit timing registers (BTR/BTR0-BTR1 or CBT) to diagnose setup violations against ISO 11783-4 requirements
- ✓ Apply propagation delay budgeting to verify compliance for multi-node VT networks with mixed cable lengths and stubs
- ✓ Explain how oscillator drift at 25°C vs. 85°C impacts timing margin in agricultural VT deployments
- ✓ Design a compliant CAN timing configuration for a 250 kbps VT network with three ECUs and 40 m total bus length
📖 Why This Matters
In precision agriculture and off-road machinery, a single CAN timing violation can cause a VT display to freeze during implement calibration—or worse, drop a critical 'stop implement' command. Unlike generic CAN networks, ISOBUS VT sessions require strict timing adherence to maintain synchronized state machines across ECU, VT, and TS (Task Controller). Timing violations are among the top three root causes of VT interoperability failures logged by ISO 11783 conformance test labs—and yet they’re often misdiagnosed as software bugs or wiring faults. Mastering this diagnosis prevents costly field rework and accelerates certification.
📘 Core Principles
CAN timing is governed by four key segments per bit: Sync_Seg (always 1 TQ), Prop_Seg (compensates for physical propagation delay), Phase_Seg1 and Phase_Seg2 (allow resynchronization). The Sample Point—the moment the bus level is read—must fall between 75%–90% of the nominal bit time per ISO 11783-4 Annex D. Violations arise when oscillator tolerance (±1.58% max for Class B VT nodes), cable-induced delay (5 ns/m typical), stub length (>0.3 m degrades timing margin), or register misconfiguration shift the actual sample point outside this window. Multi-drop VT networks compound error because each node contributes oscillator jitter and propagation asymmetry—making worst-case analysis essential, not just nominal calculation.
📐 Bit Time and Sample Point Calculation
The nominal bit time (T_bit) is determined by the CAN clock frequency and prescaler setting. The sample point (SP) is calculated as the ratio of time before sampling to total bit time. Accurate SP positioning ensures robust reception under voltage/temperature drift and EMI.
💡 Worked Example
Problem: A VT node uses a 16 MHz crystal oscillator, BRP = 4, TSEG1 = 12, TSEG2 = 5, SJW = 2. Ambient temperature is 70°C. Calculate nominal sample point and verify against ISO 11783-4 requirement (75–90%).
1.
Step 1: Compute TQ duration = (BRP + 1) / f_osc = (4 + 1) / 16,000,000 = 312.5 ns
2.
Step 2: Compute nominal bit time = (1 + TSEG1 + TSEG2 + 1) × TQ = (1 + 12 + 5 + 1) × 312.5 ns = 19 × 312.5 ns = 5937.5 ns
3.
Step 3: Compute time to sample point = (1 + TSEG1) × TQ = (1 + 12) × 312.5 ns = 13 × 312.5 ns = 4062.5 ns
4.
Step 4: Compute SP = 4062.5 / 5937.5 = 0.684 → 68.4% — violates ISO minimum 75%
5.
Step 5: Adjust TSEG1 to 14 → SP = (1 + 14) × 312.5 / (1 + 14 + 5 + 1) = 4687.5 / 6562.5 = 0.714 (71.4%) — still low; increase TSEG1 to 16 → SP = (1 + 16) × 312.5 / (1 + 16 + 5 + 1) = 5312.5 / 7187.5 = 0.739 (73.9%); final adjustment: TSEG1 = 17 → SP = 5625 / 7500 = 0.75 → exactly meets minimum.
Answer:
The result is 75.0%, which meets the ISO 11783-4 minimum safe limit of 75%.
🏗️ Real-World Application
During ISO 11783 conformance testing of a Tier 4-compliant sprayer VT system, intermittent ‘VT not responding’ errors occurred only above 60°C ambient. Oscilloscope capture revealed bit edge smearing and late sampling. Root cause analysis showed the VT’s MCU used a ±2.0% ceramic oscillator (exceeding ISO 11783-4’s ±1.58% Class B limit) and TSEG1 was set to 11 instead of minimum required 13 for 250 kbps at 40 m bus length. Corrective action: replaced oscillator with ±1.0% TCXO and updated BTR register to TSEG1=15, TSEG2=6, achieving 78.2% SP with 12.3% timing margin at 85°C—passing all thermal stress tests.